1. Field of the Invention
The present invention generally relates to a semiconductor memory device, and more particularly, to a semiconductor memory device conducting a high-speed page-mode read operation.
2. Description of the Background Art
With improvement in performance of microprocessors and the like, semiconductor memory devices including random access memories (RAMs) have been strongly required to have both increased capacity and speed.
FIG. 16 is a schematic block diagram showing the structure associated with the read operation of a conventional typical semiconductor memory device.
Referring to FIG. 16, a conventional semiconductor memory device 100 includes a memory cell array 10 having a plurality of memory cells arranged in a matrix. For example, memory cell array 10 is divided into eight data blocks DB0 to DB7. Note that, hereinafter, each data block DB0 to DB7 is sometimes generally referred to as data block DB.
An address signal Add used for address selection in memory cell array 10 is input from the outside as a 16-bit signal of address bits A0 to A15. The address bits A0 to A9 of the address signal Add select a memory cell row, whereas the address bits A10 to A15 select a memory cell column. A row address buffer 20 receives the address bits A0 to A9 used for row selection. A column address buffer 30 receives the address bits A10 to A15 used for column selection.
Row address buffer 20 and column address buffer 30 produce an internal address signal Add corresponding to the externally input address bits A0 to A15. The internal address signal Add has internal address bits a0 to a15. The internal address bits a0 to a9 are transmitted to a row decoder 40, whereas the internal address bits a10 to a15 are transmitted to a column decoder 50.
Row decoder 40 selectively activates a word line WL (not shown) provided for each memory cell row, according to the internal address bits a0 to a9. Thus, a memory cell row according to the internal address bits a0 to a9 is selected in each data block DB.
In each data block, m bit lines BL (not shown) are provided corresponding to the respective memory cell columns (where m is a natural number).
Semiconductor memory device 100 further includes column selection circuits YG0 to YG7 and sense amplifier circuits SA0 to SA7 provided corresponding to the respective data blocks DB0 to DB7. Note that, like data block DB, each sense amplifier circuit and each column selection circuit are hereinafter sometimes generally referred as sense amplifier circuit SA and column selection circuit YG, respectively.
Each column selection circuit YG selects a single bit line BL in the corresponding data block DB according to the internal address bits a10 to a15, and couples that bit line BL to the corresponding sense amplifier circuit SA. For example, column selection circuit YG0 selects one of the m bit lines BL provided in data block DB0, and couples the bit line BL to sense amplifier circuit SA0.
Semiconductor memory device 100 further includes an address transition detection circuit (hereinafter, simply referred to as an ATD generation circuit) 60. ATD generation circuit 60 receives the internal address bits a0 to a15, and activates an address transition detection signal/ATD as one-shot pulse for a prescribed period when the signal level of at least one internal address bit is changed.
Each sense amplifier circuit SA conducts a bit-line precharging operation in response to activation of tie address transition detection signal/ATD. When the address transition detection signal/ATD is inactivated thereafter, the voltage on the precharged bit line changes according to the data stored in the memory cells connected to the bit line.
Sense amplifier circuits SA0 to SA7 sense such a change in voltage on the corresponding bit line, and outputs read data SD0 to SD7, respectively. The read data SD0 to SD7 is transmitted to an output buffer 70. Output buffer 70 buffers the read data SD0 to SD7 from sense amplifier circuits SA0 to SA7, and outputs the data to the outside as output data D0 to D7 of semiconductor memory device 100.
FIG. 17 is a diagram illustrating column selection in semiconductor memory device 100.
Referring to FIG. 17, column selection circuits YG provided corresponding to the respective data blocks DB conduct m: 1 column selection. Each column selection circuit YG has m column selection switches YS0 to YSmxe2x88x921 provided corresponding to m bit lines BL1 to BLm-1, respectively. Column selection switches YS0 to YSmxe2x88x921 are respectively turned ON in response to activation of column selection signals Y0 to Ymxe2x88x921. Column decoder 50 selectively activates one of the m column selection signals Y0 to Ymxe2x88x921 according to combination of the signal levels of the internal address bits a10 to a15.
Each column selection circuit YG couples one of the m bit lines BL1 to BLmxe2x88x921 to the corresponding sense amplifier circuit SA. Sense amplifier circuit SA precharges that bit line in response to activation of the address transition detection signal/ATD, in order to read new data. The address transition activation signal/ATD is inactivated again after a prescribed period. Therefore, sense amplifier circuit SA senses a change in voltage caused by the memory cells connected to the precharged bit line, thereby outputting the read data SD.
FIG. 18 is a timing chart illustrating the read operation of semiconductor memory device 100.
Referring to FIG. 18, addresses #A0 to #A6 are sequentially selected by the address signal Add. The address transition detection signal/ATD is activated in response to address transition. In response to respective activation of the address transition detection signal/ATD, sense amplifier circuits SA0 to SA7 conduct a new data read operation, thereby outputting read data groups #SD0 to #SD6 corresponding to the addresses #A0 to #A6, respectively.
Output buffer 70 buffers the read data groups #SD0 to #SD7, thereby outputting the output data groups #D0 to #D7, respectively.
Current consumption of the read operation is given by the sum of a charging current Ich for charging the bit line in response to activation of the address transition detection signal/ATD, and a stationary current Ice consisting of a current steadily consumed by the sense amplifier and a memory cell current flowing into the memory cells upon reading the data.
In the conventional semiconductor memory device, the data reading speed is dependent on a memory cell current flowing into the memory cells upon reading the data, and a bit-line load for charging the bit line. Therefore, cell-size reduction for increased capacity and increase in data reading speed are opposed to each other, whereby the increase in data reading speed has been limited.
Such a problem is conventionally overcome by the page-mode reading. In general, the page-mode reading is a read operation in which a plurality of memory cells are accessed by sequentially changing the column while the row selection is fixed.
Fig 19 is a schematic block diagram showing the structure associated with the read operation of a conventional semiconductor memory device 110 for conducting the page-mode read operation at 2 bytes/page.
Referring to FIG. 19, in semiconductor memory device 110, each data block DB0 to DB7 is divided into two sub data blocks in order to conduct the page-mode reading. For example, data block DB0 is divided into two sub data blocks SDB0a and SDB0b. Note that, hereinafter, each sub data block is sometimes generally referred to as sub data block SDB.
Moreover, one of the two sub data blocks of each data block, i.e., SDB0a to SDB7a, is hereinafter sometimes generally referred to as sub data block SDBa, whereas the other of the two sub data blocks of each data block, i.e., SDB0b to SDB7b, is sometimes generally referred to as sub data block SDBb.
A column selection circuit YG and a sense amplifier circuit SA are provided for each sub data block. For example, in data block DB0, a sense amplifier circuit SA0a and a column selection circuit YG0a are provided for sub data block SDB0a, whereas a sense amplifier circuit SA0b and a column selection circuit YG0b are provided for sub data block SDB0b. 
Hereinafter, each sense amplifier circuit SA0a to SA7a and each column selection circuit YG0a to YG7a provided for sub data blocks SDBa are sometimes generally referred to as sense amplifier circuit SAa and column selection circuit YGa, and each sense amplifier circuit SA0b to SA7b and each column selection circuit YG0b to YG7b provided for sub data blocks SDBb are sometimes generally referred to as sense amplifier circuit SAb and column selection circuit YGb, respectively.
In semiconductor memory device 110, address bits A1 to A6 of address bits A0 to A16 are used for memory cell column selection, whereas the address bits A7 to A16 are used for memory cell row selection. Address bit A0 is used for selecting one of two sub data blocks in each data block.
Semiconductor memory device 110 includes a column decoder 51 for conducting a decode operation corresponding to the least significant address bit A0, and a column decoder 50 for decoding the remaining address bits A1 to A6 used for column selection
Sense amplifier circuits SA0a to SA7b corresponding to the sub data blocks SDB0a to SDB7b respectively output read data SD0a to SD7b. 
Semiconductor memory device 110 further includes multiplexers MX0 to MX7 provided corresponding to the respective data blocks DB0 to DB7. Hereinafter, each multiplexer MX0 to MX7 is sometimes generally referred to as multiplexer MX.
Each multiplexer MX selectively outputs one of a plurality of sense amplifier data received from the two sense amplifier circuits of the corresponding data block DB. An output buffer 70 buffers read data SD0 to SD7 selectively output from multiplexers MX, and then outputs the data to the outside of semiconductor memory device 110 as output data D0 to D7.
FIG. 20 is a diagram illustrating column selection in semiconductor memory device 110.
Referring to FIG. 20, each sub data block SDBa, SDBb includes j bit lines BL0 to BLjxe2x88x921 selected according to internal address bits a1 to a6 (where j is a natural number). Column decoder 50 selectively activates one of j column selection signals Y2 to Yj+1 according to the internal address bits a1 to a6.
Each column selection circuit YGa has a plurality of column selection switches provided between the sense amplifier circuit SAa and the respective bit lines BL0 to BLjxe2x88x921 and turned ON in response to the respective column selection signals Y2 to Yj+1. Thus, in each sub data block SDBa, a single bit line selected according to the internal address bits a1 to a6 is coupled to the corresponding sense amplifier circuit SAa.
Similarly, each column selection circuit YGb has a plurality of column selection switches provided between the sense amplifier circuit SAb and the respective bit lines BL0 to BLjxe2x88x921 and turned ON in response to the respective column selection signals Y2 to Yj+1. Thus, in each sub data block SDBb, a bit line selected according to the internal address bits a1 to a6 is similarly coupled to the corresponding sense amplifier circuit SAb.
In response to an address transition detection signal/ATD, sense amplifier circuits SAa and SAb conduct a new data read operation based on the change in voltage on the bit line selectively coupled thereto. Sense amplifier circuits SAa and SAb respectively output read data SDa and SDb.
Accordingly, each data block DB outputs two read data SDa and SDb in parallel.
Each multiplexers MX has a plurality of column selection switches coupled between the output buffer 70 and the respective sense amplifier circuits SAa and SAb and operating in response to the respective column selection signals Y0 and Y1.
Column decoder 51 activates one of the column selection signals Y0 and Y1 according to the level of the least significant internal address bit a0. Therefore, each multiplexer MX transmits one of the read data SDa and SDb to output buffer 70 as read data SD from the corresponding data block DB.
FIG 21 is a timing chart illustrating the read operation of semiconductor memory device 110.
Referring to FIG. 21, in the 2-byte/page page-mode read operation, successively input two address signals ADD such as addresses #A0 and #A1 are different from each other only in the least significant address bit A0. As a result, only a column to be selected can be changed by the successively input two addresses.
Hereinafter, the period during which a plurality of address signals ADD having common upper bits are input is also referred to as an xe2x80x9caddress cycle.xe2x80x9d In the same address cycle, the address bits except for the least significant address bit A0, i.e., the address bits A1 to A16, are the same. For example, the addresses #A0 and #A1 form the same address cycle.
Every tie the address cycle is updated, the address transition detection signal/ATD is activated in a one-shot manner.
The address transition detection signal/ATD is activated according to the input of a new address #A0. In response to this, in each data block DB, sense amplifier circuits SA0a to SA7a read a read data group #SD0 corresponding to the address #A0, and sense amplifier circuits SA0b to SA7b read a read data group #SD1 corresponding to the address #A1.
Multiplexers MX0 to MX7 transmit one of the read data groups #SD0 and #SD1 to output buffer 70 according to the least significant address bit A0. Therefore, output data groups #D0 and #D1 respectively corresponding to the addresses #A0 and #A1 can be successively output in response to the change in the address signal Add. The page-mode reading in the address cycle started corresponding to the input of an address #A2, #A4, #A6 is conducted similarly.
In such page-mode reading, two sense amplifier circuits SAa and SAb corresponding to the respective sub data blocks SDB operate in parallel in each data block DB, so that the data read operations corresponding to two internal addresses of the same address cycle are conducted in parallel. Therefore, the output data in response to switching of the address bit A0 (corresponding to the data groups #D1, #D3, #D5, #D7 in FIG. 21) can be read at a high speed. Accordingly, the normal access similar to that of semiconductor memory device 100 shown in FIG. 16 and the rapid access are alternately present, whereby the overall data reading speed of semiconductor memory device 110 can be increased.
In semiconductor memory device 110 for conducting the 2-byte/page page-mode reading, the number of sense amplifiers to be operated and the number of bit lines to be coupled to the sense amplifier circuit are both twice those of semiconductor memory device 100 shown in FIG. 16. Therefore, the bit-line charging current is increased to 2xc2x7Ich, and the stationary current also increased to 2xc2x7Ice.
In the 2-byte/page page-mode reading, an address changes only once within the same address cycle. Therefore, it is difficult to increase the data reading speed dramatically. Accordingly, the number of addresses to be successively input in the same address cycle is increased. For example, a semiconductor memory device has been developed which conducts the page-mode reading at 4 bytes/page by using the lower two bits of internal address bits.
FIG. 22 is a schematic block diagram illustrating the structure associated with the read operation of a semiconductor memory device 120 for conducting the page-mode reading at 4 bytes/page.
Referring to FIG. 22, semiconductor memory device 120 is different from semiconductor memory device 110 for conducting the 2-byte/page page-mode reading in that each data block DB0 to DB7 is divided into four sub data blocks. For example, data block DB0 is divided into sub data blocks SDB0a to SDB0d. In each data block, four column selection circuits and four sense amplifier circuits are provided corresponding to the respective sub data blocks.
Each multiplexer MX selectively outputs one of a plurality of sense amplifier data received from the four sense amplifier circuits of the corresponding data block DB. An output buffer 70 buffers the read data SD0 to SD7 selectively output from multiplexers MX, and outputs the data to the outside of semiconductor memory device 110 as output data D0 to D7.
A column decoder 51 switches data selection in each multiplexer MX according to the lower two bits a0 and a1 of internal address bits.
FIG. 23 is a diagram illustrating the column selection operation in semiconductor memory device 120 of FIG. 22. Since column selection is conducted similarly in each data block DB, FIG. 23 exemplary shows column selection in data block DB0.
In each sub data block SDB0a to SDB0d, k bit lines BL0 to BLkxe2x88x921 that are selected according to the internal address bits a2 to a6 are provided (where k is a natural number). A column decoder 50 selectively activates one of k column selection signals Y4 to Yk+3 according to the internal address bits a2 to a6.
A column selection circuit YG0a has a plurality of column selection switches provided between the sense amplifier circuit SA0a and the respective bit lines BL0 to BLkxe2x88x921 and turned ON in response to the respective column selection signals Y4 to Yk+3. Thus, in sub data block SDB0a, a single bit line selected according to the internal address bits a2 to a6 are coupled to sense amplifier circuit SA0a. 
Column selection circuits YG0b to YG0d have the same structure. Accordingly, in data blocks SDB0a to SDB0d, the bit lines selected according to the internal address bits a2 to a6 are respectively coupled to the corresponding sense amplifier circuits SA0a to SA0d. 
In response to an address transition detection signal/ATD, sense amplifier circuits SA0a to SA0d conducts a new data read operation based on the change in voltage on the bit line selectively coupled thereto. Sense amplifier circuits SA0a to SA0d respectively output read data SD0a to SD0d. Accordingly, in data block DB0, four read data SD0a to SD0d are output in response to a single internal address signal Add.
Multiplexer MX0 has a plurality of column selection switches coupled between the output buffer 70 and the respective sense amplifier circuits SA0a to SA0d and operating in response to the respective column selection signals Y0 to Y3.
Column decoder 51 activates one of the column selection signals Y0 to Y4 according to the level of the lower internal address bits a0 and a1. Accordingly, multiplexer MX0 transmits one of the read data SD0a to SD0d to output buffer 70 as read data SD0 from data block DB0.
FIG. 24 is a timing chart illustrating the read operation of semiconductor memory device 120 of FIG. 22.
Referring to FIG. 24, in the 4-byte/page page-mode operation, four address signals ADD are successively input within the same address cycle The four address signals ADD are different from each other in the lower two bits A0 and A1 of their address bits. For example, the address bits A0 and A1 contained in the four address signals of the same cycle change in the following order: (A0, A1)=(0, 0), (0, 1), (1, 0) and (1, 1).
In the same address cycle, the address bits except for the lower two bits A0 and A1, i.e., the address bits A2 to A16, are the same. For example, addresses #A0 to #A3 forming the amine address cycle are different from each other only in combination of the levels of the address bits A0 and A1.
Every time the address cycle is updated, the address transition detection signal/ATD is activated in a one-shot manner.
The address transition deflection signal/ATD is activated in response to the input of a new address #A0. In response to this, in each data block DB, sense amplifier circuits SA0a to SA7a read a read data group #SD0 corresponding to the address #A0, and sense amplifier circuits SA0b to SA7b read a read data group #SD1 corresponding to the address #A1. Moreover, sense amplifier circuits SA0c to SA7c read a read data group #SD2 corresponding to the address #A2, and sense amplifier circuits SA0d to SA7d read a read data group #SD3 corresponding to the address #A3.
Multiplexers MX0 to MX7 transmit one of the read data groups #SD0 to #SD3 to output buffer 70 according to internal address bits a0 and a1 respectively corresponding to the address bits A0 and A1. Therefore, output data groups #D0 to #D3 respectively corresponding to the addresses #A0 to #A3 can be successively output in response to the change in address. The page-mode reading is conducted similarly in the following address cycle formed by addresses #A4 to #A7.
Thus, in each data block DB, four sense amplifier circuits respectively corresponding to the sub data blocks are operated in parallel, so that the data corresponding to the four internal addresses of the same address cycle are read in parallel. Therefore, the data output (corresponding to the output of the data groups #D1, #D2, #D3, #D5, #D6, #D7 in FIG. 21) in response to switching of the lower two address bits A0 and A1 can be conducted at a high speed. Accordingly, the rate of the data that is output by the rapid access is increased as compared to semiconductor memory device 110 for conducting the 2-byte/page page-mode reading, whereby the overall data reading speed of semiconductor memory device 120 can further be increased.
The number of sense amplifiers to be operated simultaneously and the number of bit lines to be coupled to the sense amplifier circuits are four times those of semiconductor memory device 100 shown in FIG. 16. Therefore, the 4-byte/page page-mode reading is conducted with increased current consumption. More specifically, the charging current is increased to 4xc2x7Ich, and the memory cell current is increased to 4xc2x7Ice. Thus, although the page-mode operation increases the data reading speed, it also increases the current consumption.
As described above, the page-mode reading increases the data reading speed by increasing the number of addresses successively input within the same address cycle. However, this correspondingly increases the number of sense amplifier circuits, resulting in an increased layout area. Moreover, the number of sense amplifier circuits to be operated simultaneously and the number of bit lines to be coupled to the sense amplifier circuits in the data read operation are also increased. Therefore, the increased data reading speed correspondingly increases the current consumption.
It is an object of the present invention to reduce the current consumption and the layout area in a semiconductor memory device for conducting the page mode reading.
In summary, according to the present invention, a semiconductor memory device for conducting data output in response to K addresses from first to Kth addresses having at least one bit in common (where K is a natural number; Kxe2x89xa72) includes a data block, a plurality of sense amplifier circuits, a first data selection circuit, a second data selection circuit, a decode circuit, and a third data selection circuit.
The data block has a plurality of memory cells arranged in a matrix, and is divided into N sub data blocks (where N is a natural number; Nxe2x89xa72). The plurality of sense amplifier circuits are provided corresponding to the respective sub data blocks, and amplify the read data transmitted thereto. N first data selection circuits and N second data selection circuits are provided corresponding to the respective sub data blocks. Each of the first data selection circuits selects L read data from a corresponding one of the N sub data blocks according to at least one bit of the addresses, and outputs the selected L read data (where L is a natural number given by K/N). Each of the second data selection circuits selects one of the L read data from a corresponding one of the N first data selection circuits, and transmits the selected read data to a corresponding one of the N sense amplifier circuits. The decode circuit switches selection of the read data in the N second data selection circuits according to the addresses. The third data selection circuit is provided corresponding to the data block, and receives the N read data respectively amplified by the N sense amplifier circuits, and selectively outputs the read data corresponding to the addresses.
Accordingly, the present invention is mainly advantageous in that the page-mode reading can be conducted in which a larger number of addresses than that of sense amplifier circuits are successively accessed. As a result, high-speed page-mode reading can be conducted with reduced power consumption and layout area of the sense amplifier circuits.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.